circuit emitter :
  extmodule BUFG :
    input I : Clock
    output O : Clock
    defname = BUFG

  module emitter :
    output io : { flip systemclk : Clock, flip systemRstn : UInt<1>, flip enable : UInt<1>, emitterio : { flip fpga_cim_data : UInt<2>, flip fpga_cim_cmd : UInt<1>, cim_fpga_state : UInt<1>, cim_fpga_result : UInt<8>}, flip chipio : { flip fpga_cim_data : UInt<2>, flip fpga_cim_cmd : UInt<1>, cim_fpga_state : UInt<1>, cim_fpga_clk : Clock, cim_fpga_result : UInt<8>}}

    node systemRst = eq(io.systemRstn, UInt<1>("h0")) @[emitter.scala 34:19]
    reg data : UInt, io.systemclk with :
      reset => (systemRst, UInt<1>("h0")) @[Reg.scala 28:20]
    when io.enable : @[Reg.scala 29:18]
      data <= io.emitterio.fpga_cim_data @[Reg.scala 29:22]
    reg cmd : UInt<1>, io.systemclk with :
      reset => (systemRst, UInt<1>("h0")) @[Reg.scala 28:20]
    when io.enable : @[Reg.scala 29:18]
      cmd <= io.emitterio.fpga_cim_cmd @[Reg.scala 29:22]
    io.chipio.fpga_cim_data <= data @[emitter.scala 38:33]
    io.chipio.fpga_cim_cmd <= cmd @[emitter.scala 39:33]
    inst BUFG of BUFG @[emitter.scala 41:22]
    BUFG.O is invalid
    BUFG.I is invalid
    BUFG.I <= io.chipio.cim_fpga_clk @[emitter.scala 42:12]
    reg state : UInt<1>, BUFG.O with :
      reset => (systemRst, UInt<1>("h0")) @[Reg.scala 28:20]
    when io.enable : @[Reg.scala 29:18]
      state <= io.chipio.cim_fpga_state @[Reg.scala 29:22]
    reg result : UInt, BUFG.O with :
      reset => (systemRst, UInt<1>("h0")) @[Reg.scala 28:20]
    when io.enable : @[Reg.scala 29:18]
      result <= io.chipio.cim_fpga_result @[Reg.scala 29:22]
    io.emitterio.cim_fpga_state <= state @[emitter.scala 46:35]
    io.emitterio.cim_fpga_result <= result @[emitter.scala 47:35]

